This invention relates to a circuit for creating a pulse output signal each time that an erasable-programmable-array-logic (EPAL) integrated circuit is energized by a source of power and for delaying transmission of that presetting pulse to individual logic elements of that inegrated circuit.
Control logic circuits that use some form of storage element, such as a register or a set-reset flip-flop, generally need an initialization signal pulse. The initialization or "power-up" signal pulse is necessary to force the output of each such storage element to a predetermined condition, either a "1" or a "0", immediately or shortly after the logic circuit power is switched ON from the OFF state. Forcing the storage elements to a predetermined condition tends to prevent unpredictable and unwanted operations that sometimes occur during or shortly after the time interval required for the voltage at the power supply input terminal to rise to a steady-state value of voltage. Such unpredictable operations include spurious write cycles in an electrically-programmable-read-only-memory (EPROM) cell and include illegal states of a finite-state machine implemented by a set of EPAL logic arrays.
An example of a prior-art circuit for creating a "power up" pulse signal is illustrated in U.S. Pat. No. 4,716,322, issued to Sebastiano D'Arrigo, Giuliano Imondi and Sossio Vergara, and assigned to Texas Instruments Incorporated. The circuit described in that patent requires a clock input, a separate reference voltage input, and two resistors formed on an integrated-circuit substrate. A circuit that eliminates the need for a clock input, a separate reference voltage input, and resistor fabrication is desirable.